CMOS device is often
portrayed to be an impeccable device, especially in the textbooks. There are
some innate problems in the CMOS device and one of them is the latch-up. We're
gonna talk about it in detail.
Consider the cross-section of a CMOS inverter. Please note that I have skipped drawing some metal layers and contacts for the sake of simplicity. My focus is on explaining the problem of latch-up and not the layout design rules!
Consider the cross-section of a CMOS inverter. Please note that I have skipped drawing some metal layers and contacts for the sake of simplicity. My focus is on explaining the problem of latch-up and not the layout design rules!
Figure 1: CMOS with
parasitic BJTs
In the above
cross-section, note that 1-2-3 form a parasitic pnp type bipolar junction
transistor, while 4-3-2 form a parasitic npn bipolar junction transistor. Since
parasitic transistors would be present in every CMOS device! A simplistic
figure depicting these parasitic transistors is given below:
Figure 2: Simplistic
Figure depicting parasitic BJTs
Here, the npn and the
pnp transistors are depicted with 2 and 3 being common between the two
transistors. Also note that the n-well layer and the p-substrate ate lightly
doped layers, and hence offer greater resistance as compared to the n+, p+
drain and source regions. The n-well resistance of PMOS is depicted by the
resistor R2 and the resistance of p-substrate is depicted by the resistor R1.
Let's say, we've got a spike at the output of
the CMOS inverter.
1. This is a
negative spike (or a bump), which decreases the potential of VOUT below ground
potential by 0.7V.
2. As a
result, the npn transistor 4-3-2 gets turned ON, and the emitter (n+, 4) starts
emitting electrons, which eventually get collected at the collector (n-well, 2)
and go into VDD.
3. The
current hence flows in the reverse direction from the n+ body towards the
n-well region.
4. We will
have a voltage drop in the direction of current, as a result the potential at
the n-well can reach 0,7V below VDD. This turns the pnp transistor ON,
because p+ region emitter is at VDD!
5. The
current is collected at the collector (p-substrate, 3) and flows into the
ground through the p+ body region.
6. Going
opposite to the direction of current, the potential difference increases, and
the voltage at p-substrate (just below the n+ of NMOS, might reach 0.7V,
thereby injecting more current!
Figure 3: Sequence of
events leading to latch-up
As evident from the above steps, just one spike at the output
initiates a chain reaction resulting in current flow through the device
incessantly, and hence the device gets worn out in a very short span of time!
This is the latch-up!
How to mitigate the problem?
Well, as we just noticed, the main cause of latch-up was the
resistance of n-well and the p-substrate layers. Hence, the most logical
solution would be to increase their doping concentration by ion implantation.
But that would deteriorate the transistor operation! Remember, we need to keep
the doping of wells and substrate low; while those of source and drain high yo
ensure a good transistor operation.
What do we do now?
Well, we shall stick with ion implantation, but instead of doing
it near the silicon surface and hence near the drain and source, implant a deep
n-well with high doping concentration, and similarly, implant a deep p-well
inside the p-substrate to reduce the resistance and hence kill the parastic BJT
action!
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