Factors Affecting Delays of Standard Cells in VLSI

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In this post, we would talk about the factors that affect the delays of standard cells.

Before starting with the discussion, it would be prudent to discuss what is meant byTiming Arcs:

Timing Arcs:

A timing arc represents the direction of the signal flow from usually an input to an output.

They may be combinational or sequential. Combinational arcs represent the signal flow in combinatorial cells like AND, NAND, OR gates. Sequential arcs represents the signal flow in Flip Flops and they usually have a control signal like CLOCK associated with them. Third type that is closely related to sequential arcs are the setup and hold arcs. They represent the setup and hold requirements and in general, do not represent any signal flow. 

The information about these timing arcs come from the timing library (.lib) files.

Let's turn our attention back to delays.

Consider an AND gate. As discussed above, A to Z is a combinational timing arc. The delay of this arc is picked up from the .lib. This .lib is then read by the timing tools in timing reports.

This delay depends on primarily 2 factors:

1. The input slew or the transition at A pin.

2. The output load or the capacitance at the Z pin.

Note that the output load is the sum total of the input capacitance of the cells connected to the node Z and also the net capacitance of all such nodes.

Output Load = Input Cap of all cells at the fan-out of Z + Total net capacitance of the nets connected to node Z.

Delay is directly proportional to the input transition and the output load.

• More is the output cap, more time the cell would require to charge/discharge that capacitance. And hence,  delays would be more. 
• More is the input transition, more time the cell would require to change the output after processing the input value.

You would note that explanation behind delays just boil down to charging/discharging of the capacitors!! Once you befriend them, you would be able to deduce half the concepts intuitively. 

We are now set to discuss the delays of timing arcs of a flip-flop.

1. Clock-to-Q delay: As expected, it depends upon the clock transition and the load at the output Q. It may sound surprising, but clock-to-q delay does not depend upon the transition at the D input.

2. Setup and Hold time: Setup and Hold time depend upon the transition value at clock pin and transition value at D pin. It does not depend on the output load.

Some surprises might be yet to unfold. Read on.

·         Clock-to-q delay is directly proportional to the clock transition and the output cap at Q.

·         Setup time is directly proportional to input transition at D and inversely proportional to the clock transition. Recall the definition of setup time. More is the clock transition time, more time you are allowing for the input at D to settle setup-time before the clock transition.

·         Hold time is inversely proportional to input transition at D and directly proportional to the clock transition. Again, recall the definition of hold time. More is the clock transition time, greater is the possibility that the D input might change in the hold window after clock transition.

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