Static random access memory (SRAM) Structure: SRAM provide static random access memory implementation. Here 6 transistors are used to store bits of data. SRAM 6T form L1 data cache in microprocessor as they have short access time, they are able to retain data for 10’s of microsecond. Current level of device miniaturizations makes it very difficult to model 6T SRAM memories with required level of reliability 6T SRAM also suffers from instability which results in performance reduction, which helps in gaining technology scaling. [3]. Process variation directly attaches the weakness of 6T SRAM producing transistors that deviate from their sizes , thereby causing device mismatches .Process variation directly attaches the weakness of 6T SRAM producing transistors that deviate from their sizes ,thereby causing device limits 6T performance scalability by causing variation in operating speed of individual cells and memory lines. 
Process variation affects speed of 6T SRAM. Figure shows schematic of standard 6T cell. To
perform read operation pre-charging of both bit-lines, strobing word line and seeing which bitline discharges. If inverted then ‘1’ is read if regular then ‘0’.Variation in gate length and
threshold voltages of these transistors changes current driving capabilities. Process variation also
attacks the stability of a 6T SRAM cell. For example, transistor T2 is designed to be very strong,
transistor T1, moderately strong, and transistor T3, weak.

1T1C DRAM Cell:
                             The information is stored as different charge levels at a capacitor in conventional 1T/1C DRAM. The advantage of using DRAM is that it is structural simple: only one transistor and capacitor are required for storing one bit, compared to six transistors required in SRAM. This allows DRAM to have a very high density. The DRAM industry has advanced over a period of time in packing more and more memory bits per unit area on a silicon die. But, the scaling for the conventional 1Transistor/1Capacitor (1T/1C) DRAM is becoming increasingly difficult, in particular due to a capacitor has become harder to scale, as device geometries shrink. Apart from the problems associated with the scaling of the capacitor, scaling also introduces yet another major problem for the DRAM manufacturers which is the leakage current.

4T DRAM Cell:
                 The cell structure shown in fig. 3 is a 4T DRAM cell structure. This DRAM cell design consists of four transistors. One transistor is used as a write transistor, the other as a read transistor. Data in DRAM is stored in the form of charge at the capacitance attached with the transistor structure. There is no current path to the storage node for restoring the data; hence data is lost due to leakage with the period of time. Read operation for the 4T DRAM cell is non-destructive, as the voltage at the storage node is maintained.

3T DRAM Cell:
                    The simplest DRAM cell is the 3T scheme. A 3T DRAM cell has a higher density than a SRAM cell; moreover in a 3T DRAM, there is no constraint on device ratios and the read operation is nondestructive. In this cell, the storage capacitance is the gate capacitance of the readout device, so making this scheme attractive for embedded memory applications; however, a 3T DRAM shows still limited performance and low retention time to severely limit its use in advanced integrated circuits.3T DRAM utilizes gate of the transistor and a capacitance to store the data value. When data is to be written, write signal is enabled and the data from the bit line is fed into the cell. When data is to be read from the cell, read line is enabled and data is read through the bit line. 3T DRAM cell occupies less area compared to the 4T DRAM cell.

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